The present invention relates to a semiconductor memory device, and more particularly, to technology of preventing errors occurring as commands are misrecognized in a semiconductor memory device.
A semiconductor memory device typically receives commands through input pads where data and addresses for designating locations of data are inputted.
Table 1 shows a command sequence of one, e.g., a NOR flash memory device, of semiconductor memory devices receiving commands through address pads ADDR and data pads DATA.
TABLE 1Command Definitioncycle1st2nd3rd4th5th6thResetADDR1XXXHDATAF0HProgramADDR4555H2AAH555HPADATAAAH55HA0HPDProgramADDR1XXXHSuspendDATAB0HProgramADDR1XXXHResumeDATA30HCFI QueryADDR1X55HDATA98HWrite toADDR3555H2AAHBABAPAWBLBufferDATAAAH55H25HWCPDPDProgramADDR1BABuffer to GSTDATA29HWrite toADDR3555H2AAHXXXHBuffer Abort ResetDATAAAH55HF0H
FIG. 1A is a timing diagram illustrating that a single program command (Program) defined in Table 1 is inputted to a memory device. FIG. 1B is a timing diagram illustrating that a buffer program command (Write to Buffer) defined in Table 1 is inputted to the memory device.
First of all, symbols in FIGS. 1A and 1B will be described hereinafter. ADDR represents a signal inputted through an address pad (pin); DATA represents a signal inputted through a data pad; and WE# represents a write enable signal enabled to a logic low to latch signals inputted through the address pad and the data pad. SPGM represents a signal enabled to a logic high when the memory device recognizes that the signal program command is inputted thereto by decoding signals inputted through the address pad and the data pad, and WT2BU represents a signal enabled to a logic high when the memory device recognizes that the buffer program command is inputted thereto by decoding signals inputted through the address pad and the data pad.
Referring to FIG. 1A, if 555H, 2AAH and 555H are inputted through the address pad ADDR for three cycles and AAH, 55H and A0H are inputted through the data pad DATA for three cycles, the memory device recognizes them as single program commands and enables the single program signal SPGM internally. Then, the memory device programs program data PD into a memory cell designated by program addresses PA that are subsequently inputted.
Referring to FIG. 1B, if 555H, 2AAH and BA are inputted through the address pad ADDR and AAH, 55H and 25H are inputted through the data pad DATA, the memory device recognizes them as buffer program commands and enables the buffer program signal WT2BU internally, wherein BA is a block address and represents a part of program addresses. When the buffer program signal WT2BU is enabled and the block address BA and a word count value WC are subsequently inputted for one cycle, the memory device receives program addresses PA_0 to PA_N and program data PD_0 to PD_N whose numbers correspond to the word count value WC. Herein, the number of program addresses/data is the number of WC+1 which is obtained by adding ‘1’ to the word count value WC. The memory device programs the program data PD_0 to PD_N into memory cells designated by the program addresses PA_0 to PA_N.
FIG. 2 illustrates a block diagram of a conventional semiconductor memory device.
Referring to FIG. 2, the semiconductor memory device includes a transfer block 210, a command decoding block 220, an address decoding block 230, a write driving block 240 and a cell array 250.
Signals inputted through a plurality of address pads ADDR, e.g., A numbers of address pads, and a plurality of data pads DATA, e.g., B numbers of data pads, responsive to a write enable signal WE#, are provided to the transfer block 210. The transfer block 210 transmits the signals inputted through the address pads ADDR to the address decoding block 230 so that the address decoding block 230 selects memory cells. The transfer block 210 transmits the signals inputted through the data pads DATA to the write driving block 240 so that the write driving block 240 writes data into the memory cells. Meanwhile, the transfer block 210 may transmit the signals inputted through the address pads ADDR and the data pads DATA to the command decoding block 220 as well.
The command decoding block 220 decodes the signals coupled from the transfer block 210 to judge which command is provided to the memory device, and generates a control signal CONTROL SIGNAL to control the write driving block 240 and circuits in a chip based on the judged results.
In the conventional semiconductor memory device, signals inputted through the address pads ADDR and the data pads DATA are continuously transferred to the command decoding block 220. Then, the command decoding block 220 judges whether or not commands are inputted to the memory device according to the command sequence described in Table 1. In such a construction, program addresses PA and program data PD may be misrecognized as commands. For instance, in a single program operation like that shown in FIG. 1A, if the program address PA of XXXH and the program data PD of B0H are inputted to the semiconductor memory device, the command decoding block 220 recognizes that a program suspend command (Program Suspend) is inputted and thus the single program operation is stopped.
That is, although addresses to designate a memory cell and data to be programmed in the designated memory cell are inputted, they may be misrecognized as commands and thus the malfunction of the semiconductor memory device may be induced.